Totem: Domain-Specific Reconfigurable Logic

FPGAs have an important role to play in System-on-a-Chip (SoC) designs by providing programmable hardware resources within complex ASIC designs. However, because the FPGA logic is custom-fabricated with the overall SoC, we have an opportunity to optimize that logic to the SoC’s specific needs. This gave rise to the Totem Project, which automates the creation of domain-specific reconfigurable logic. In this paper we present the lessons learned from the Totem Project, including how best to create domain-specific architectures, how to instantiate that logic into silicon, and how to create CAD tools to support these architectures. We also quantify how much improvement these optimizations provide over standard cells and tile-based FPGA logic. Finally, we consider the role of flexibility in domain-specific reconfigurable logic, and present strategies on how best to provide the right amount of flexibility.